Fault Tolerant Routing in Mesh Topologies

Fault tolerant routing refers to transfer of messages from a source to destination in a network with faulty links and/or nodes. Fault tolerant routing is one of the key problems in designing robust distributed algorithms. Internet routing protocols like BCG are also examples of adaptive routing algorithms. Adaptive routing in distributed systems can be desirable at either the application level (like routing in LAN) or at the harware chip level, where on chip in the circuit layout wants to communicate to another chip (for example two processors communicating intermediate results). In both these cases the main aim of the underlying routing problem differs, for example in the case of adaptive routing in LAN it is more desirable to optimize upon the number of hops or the throuhput of the network giving lesser weightage to the initial routing latency. However when it is the case of on-chip routing the optimization parameter is more likely to be the time required to route the message, the message over-head, complexity of the algorithm (as it has to be implemented at hardware level). In the case of on-chip routing, the network topology, in general, is not arbitrary but a well defined layout pattern. This enables optimization of an algorithm for the specific topology. Mesh topology is a very common circuit layout where the chips/nodes are arranged in aN×N matrix with each node connected to its immediate column and row neighbors. In this work we shall discuss and compare adaptive routing algorithms for mesh topologies to guarantee routing along the shortest path.